Semiconductor device and method of integrating power module with interposer and opposing substrates

ABSTRACT

A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.

CLAIM OF DOMESTIC PRIORITY

The present application is a continuation of U.S. patent applicationSer. No. 15/231,277, filed Aug. 8, 2016, which application isincorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and,more particularly, to a semiconductor device and method of integrating apower module with an internal interposer and opposing substrates.

BACKGROUND

Semiconductor devices are commonly found in modern electronic products.Semiconductor devices vary in the number and density of electricalcomponents. Semiconductor devices perform a wide range of functions suchas analog and digital signal processing, sensors, transmitting andreceiving electromagnetic signals, controlling electronic devices, powermanagement, and audio/video signal processing. Discrete semiconductordevices generally contain one type of electrical component, e.g., lightemitting diode (LED), small signal transistor, resistor, capacitor,inductor, diodes, rectifiers, thyristors, and powermetal-oxide-semiconductor field-effect transistor (MOSFET). Integratedsemiconductor devices typically contain hundreds to millions ofelectrical components. Examples of integrated semiconductor devicesinclude microcontrollers, application specific integrated circuits(ASIC), power conversion, standard logic, amplifiers, clock management,memory, interface circuits, and other signal processing circuits.

FIG. 1a shows a conventional semiconductor die 10 with base substratematerial 12, active surface 14, and active surface 16. An insulatinglayer 18 and interconnect pads 20 are formed over active surface 14.

Semiconductor die 10 may include a discrete power semiconductor device,such as a vertical insulated gate bipolar transistor (IGBT), diode,power MOSFET, or other power device. FIG. 1b shows a top view of activesurface 14 with an IGBT, which combines the gate-drive feature of ametal oxide semiconductor field effect transistor (MOSFET) with thehigh-current and low-saturation-voltage of a bipolar transistor. TheIGBT includes emitter regions 30 a-30 d, gate region 38, and sensorregions 40, 44, and 46, e.g., for current and temperature sensing.Active surface 16 operates as the collector of the IGBT. The IGBT issusceptible to high overshoot voltage during switching due to parasiticinductance. In addition, heat dissipation from semiconductor die 10through base substrate material 12 is generally poor, which reducesefficiency, increases operating temperature, and lower reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1a-1b illustrate a conventional discrete IGBT semiconductordevice;

FIGS. 2a-2e illustrate a semiconductor wafer with a plurality ofsemiconductor die separated by a saw street;

FIGS. 3a-3b illustrate a vertical IGBT with the interconnect padsarranged in a pattern of large pads and small pads;

FIG. 4a-4g illustrate a process of integrating a power module with aninterposer and opposing substrates;

FIG. 5 illustrates an embodiment of the integrated power module withopposing substrates; and

FIG. 6 illustrates another embodiment of the integrated power modulewith opposing substrates.

DETAILED DESCRIPTION OF THE DRAWINGS

The following describes one or more embodiments with reference to thefigures, in which like numerals represent the same or similar elements.While the figures are described in terms of the best mode for achievingcertain objectives, the description is intended to cover alternatives,modifications, and equivalents as may be included within the spirit andscope of the disclosure. The term “semiconductor die” as used hereinrefers to both the singular and plural form of the words, andaccordingly, can refer to both a single semiconductor device andmultiple semiconductor devices.

FIG. 2a shows a semiconductor wafer 100 with a base substrate material102, such as silicon, germanium, aluminum phosphide, aluminum arsenide,gallium arsenide, gallium nitride, indium phosphide, silicon carbide, orother bulk semiconductor material. A plurality of semiconductor die 104is formed on wafer 100 separated by a non-active, inter-die wafer areaor saw street 106, as described above. Saw street 106 providessingulation areas to separate semiconductor wafer 100 into individualsemiconductor die 104. In one embodiment, semiconductor wafer 100 has awidth or diameter of 100-450 millimeters (mm).

FIG. 2b shows a cross-sectional view of a portion of semiconductor wafer100. Each semiconductor die 104 has back surface 108 and active surface110 containing analog or digital circuits implemented as active devices,passive devices, conductive layers, and dielectric layers formed withinthe die and electrically interconnected according to the electricaldesign and function of the die. For example, the circuit may include oneor more transistors, diodes, and other circuit elements to implement adiscrete power semiconductor device, such as an IGBT, diode, powerMOSFET, wide bandgap or narrow bandgap semiconductor device, and otherpower device.

An electrically conductive layer 112 is formed on active surface 110, orembedded with a passivation layer over the active surface, using PVD,CVD, electrolytic plating, electroless plating process, evaporation, orother suitable metal deposition process. Conductive layer 112 includesone or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni),gold (Au), silver (Ag), titanium (Ti), titanium tungsten (TiW), or othersuitable electrically conductive material. Conductive layer 112 operatesas interconnect pads electrically connected to the circuits on activesurface 110.

An insulating or passivation layer 114 is formed over active surface 110around conductive layer 112 using PVD, CVD, printing, lamination, spincoating or spray coating. Insulating layer 114 contains one or morelayers of silicon dioxide (SiO2), silicon nitride (Si3N4), siliconoxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3),solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazoles(PBC)), polymer, or other material having similar insulating andstructural properties.

Semiconductor wafer 100 undergoes electrical testing and inspection aspart of a quality control process. Manual visual inspection andautomated optical systems are used to perform inspections onsemiconductor wafer 100. Software can be used in the automated opticalanalysis of semiconductor wafer 100. Visual inspection methods mayemploy equipment such as a scanning electron microscope, high-intensityor ultra-violet light, metallurgical microscope, or optical microscope.Semiconductor wafer 100 is inspected for structural characteristicsincluding warpage, thickness variation, surface particulates,irregularities, cracks, delamination, contamination, and discoloration.

The active and passive components within semiconductor die 104 undergotesting at the wafer level for electrical performance and circuitfunction. Each semiconductor die 104 is tested for functionality andelectrical parameters, as shown in FIG. 2c , using a test probe head 116including a plurality of probes or test leads 118, or other testingdevice. Probes 118 are used to make electrical contact with nodes orconductive layer 112 on each semiconductor die 104 and provideelectrical stimuli to interconnect pads 112. Semiconductor die 104responds to the electrical stimuli, which is measured by computer testsystem 120 and compared to an expected response to test functionality ofthe semiconductor die. The electrical tests may include circuitfunctionality, lead integrity, resistivity, continuity, reliability,junction depth, ESD, RF performance, drive current, threshold current,leakage current, and operational parameters specific to the componenttype. The inspection and electrical testing of semiconductor wafer 100enables semiconductor die 104 that pass to be designated as known gooddie for use in a semiconductor package.

In FIG. 2d , an electrically conductive bump material is deposited overconductive layer 112 using an evaporation, electrolytic plating,electroless plating, ball drop, or screen printing process. The bumpmaterial can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder,and combinations thereof, with an optional flux solution. For example,the bump material can be eutectic Sn/Pb, high-lead solder, or lead-freesolder. The bump material is bonded to conductive layer 112 using asuitable attachment or bonding process. In one embodiment, the bumpmaterial is reflowed by heating the material above its melting point toform balls or bumps 126. In some applications, bumps 126 are reflowed asecond time to improve electrical contact to conductive layer 112. Inone embodiment, bumps 126 are formed over an under bump metallization(UBM) layer. Bumps 126 can also be compression bonded orthermos-compression bonded to conductive layer 112. Bumps 126 representone type of interconnect structure that can be formed over conductivelayer 112. The interconnect structure can also use conductive pillar,stud bump, micro bump, bond wires, conductive paste, or other electricalinterconnect.

In FIG. 2e , semiconductor wafer 100 is singulated through saw streets106 with saw blade or laser cutting tool 128 or plasma etching processinto individual semiconductor die 104.

FIGS. 3a-3b illustrate semiconductor wafer 104 implemented as a verticalIGBT with the interconnect pads of conductive layer 112 arranged in anidentifiable pattern of large pads and small pads. FIG. 3a is across-section view of semiconductor die 104 with bumps 126 a-126 bconnected to the gate region, emitter regions, and sensing regions ofthe IGBT. Back surface 108 is the collector of the IGBT.

FIG. 3b is a top view of active surface 110 including insulating layer114 and interconnect pads 112 a and 112 b coupled in common to emitterregions of the IGBT. In particular, interconnect pads 112 a are largepads, e.g., 2.0 mm×2.0 mm, and interconnect pads 112 b are small pads,e.g., 0.5 mm×0.5 mm. The different areas of interconnect pads 112 a-112b provide high current carrying capacity, while reducingelectro-migration and parasitic voltage overshoot. Interconnect pads 112c are coupled to one or more sensing regions of the IBGT, andinterconnect pads 112 d are coupled to the gate region of the IGBT.Interconnect pads 112 c-112 d are small pads, e.g., 0.5 mm×0.5 mm.

Interconnect pads 112 a-112 d are arranged in an identifiable pattern,as shown in FIG. 3b , to provide accurate and reliable alignment to thenext level of integration, based on specific size and placement of largeand small interconnect pads. For example, interconnect pads 112 a can bearranged in an identifiable pattern of multiple parallel rows, or rowsof alternating offset interconnect pads. Interconnect pads 112 b can bearranged in an identifiable pattern of multiple parallel rows, orinterspersed between interconnect pads 112 a. Interconnect pads 112c-112 d can be arranged in an identifiable pattern of groups of multipleparallel or offset rows. Bumps 126 a over interconnect pads 112 a arelarger than bumps 126 b over interconnect pads 112 b-112 d.

FIGS. 4a-4g illustrate a process of forming a power integrated module(PIM) and/or intelligent power module (IPM) with an interior interposerwith vertical electrical interconnect and opposing substrates. In FIG.4a , interposer 150 includes core substrate 152 made of an insulatingmaterial, such as ceramic, glass, or polymer, with conductive vias 154formed through the core substrate for vertical electrical interconnect.Core substrate 152 can be one or more laminated layers ofpolytetrafluoroethylene pre-impregnated (prepreg), FR-4, FR-1, CEM-1, orCEM-3 with a combination of phenolic cotton paper, epoxy, resin, wovenglass, matte glass, polyester, and other reinforcement fibers orfabrics. A conductive layer 156 is formed over surface 158 of coresubstrate 152, and conductive layers 160 and 161 are formed over surface162 of core substrate 152. Conductive layers 156 and 160-161 are formedusing PVD, CVD, electrolytic plating, electroless plating process,evaporation, or other suitable metal deposition process or metal layerjoining with substrate 170 through sintering process. Conductive layers156 and 160-161 includes one or more layers of aluminum Al, Cu, Sn, Ni,Au, Ag, Ti, TiW, or other suitable conductive material. Conductivelayers 156 and 160-161 are patterned into portions that are electricallycommon or electrically isolated depending on the design and function ofsemiconductor die 104 a-104 d.

A control circuit 164 is disposed over conductive layer 156.Alternatively, a discrete semiconductor device 164 is disposed overconductive layer 156. The different portions of conductive layer 156 arecoupled to external terminals of a leadframe, control circuit ordiscrete device 164, and back surfaces 108 of semiconductor die 104a-104 b.

Semiconductor die 104 a from FIGS. 3a-3b is positioned over and alignedwith die attach area 166 of interposer 150. Semiconductor die 104 b fromFIGS. 3a-3b is positioned over and aligned with die attach area 168 ofinterposer 150. Semiconductor die 104 a-104 b can each be a same type ordifferent type of discrete semiconductor device, such as an IGBT, diode,power MOSFET, wide bandgap or narrow bandgap semiconductor device, andother power device. In the case of an IGBT, back surface 108 ofsemiconductor die 104 a is the collector and makes electrical connectionto conductive layer 156 within die attach area 166, and back surface 108of semiconductor die 104 b makes electrical connection to conductivelayer 156 within die attach area 168. Interconnect pads 112 a-112 d ofsemiconductor die 104 a-104 b can be coupled to the emitter region, gateregion, and sensing regions of the IGBT.

In FIG. 4b , substrate 170 includes core 172 made of an electricallyinsulating material, such as ceramic, glass, or polymer. Core 172 can beone or more laminated layers of prepreg, FR-4, FR-1, CEM-1, or CEM-3with a combination of phenolic cotton paper, epoxy, resin, woven glass,matte glass, polyester, and other reinforcement fibers or fabrics. Core172 is made with thermally conductive material to provide substrate 170for effective heat dissipation. Conductive layers 174 and 176 are formedover surface 178 of core material 172, and conductive layer 180 isformed over surface 182 of core material 172. Conductive layers 174-176and 180 are formed using PVD, CVD, electrolytic plating, electrolessplating process, evaporation, or other suitable metal deposition processor metal layer joining with substrate 170 through sintering process.Conductive layers 174-176 and 180 includes one or more layers ofaluminum Al, Cu, Sn, Ni, Au, Ag, Ti, TiW, or other suitable conductivematerial. Conductive layers 174-176 are patterned into portions that areelectrically common or electrically isolated depending on the design andfunction of semiconductor die 104 a-104 d. The different portions ofconductive layer 174-176 are coupled to bumps 126 a-126 b overinterconnect pads 112 a-112 d of semiconductor die 104 c-104 d andexternal terminals of a leadframe.

Semiconductor die 104 c from FIGS. 3a-3b is positioned over and alignedwith die attach area 186 of substrate 170. Semiconductor die 104 d fromFIGS. 3a-3b is positioned over and aligned with die attach area 188 ofsubstrate 170. Semiconductor die 104 c-104 d can each be a same type ordifferent type of discrete semiconductor device, such as an IGBT, diode,power MOSFET, wide bandgap or narrow bandgap semiconductor device, andother power device. In the case of an IGBT, back surface 108 ofsemiconductor die 104 c is the collector and makes electrical connectionto conductive layer 174 within die attach area 186, and back surface 108of semiconductor die 104 d makes electrical connection to conductivelayer 176 within die attach area 168. Interconnect pads 112 a-112 d ofsemiconductor die 104 c-104 d can be coupled to the emitter region, gateregion, and sensing regions of the IGBT.

FIG. 4c shows semiconductor die 104 a-104 b mounted to interposer 150 asassembled interposer 190, and semiconductor die 104 c-104 d mounted tosubstrate 170 as assembled substrate 192. Back surfaces 108 ofsemiconductor die 104 a-104 b are bonded to conductive layer 156 in dieattach area 166 and conductive layer 156 in die attach area 168,respectively, by reflow of conductive material, Ag sintering, conductivepaste, or other electrical interconnect. Back surfaces 108 ofsemiconductor die 104 c-104 d are bonded to conductive layers 174 and176, respectively, by reflow of conductive material, Ag sintering,conductive paste, or other electrical interconnect. Assembly interposer190 is positioned over and aligned with assembled substrate 192.

FIG. 4d shows assembled thermal interposer 190 mounted to assembledsubstrate 192 as 3D stacked assembled substrates 198. The large andsmall interconnect pads 112 a-112 d of FIGS. 3a-3b provide accurate andreliable alignment and mounting of interposer 150 to semiconductor die104 c-104 d. Bumps 126 a-126 b of semiconductor die 104 c-104 d arebonded to conductive layers 160-161 of interposer 150 by a reflowprocess. The temperature and timing of the reflow process, as well asthe bonding material, is selected to prevent debonding back surfaces 108of semiconductor die 104 a-104 d from conductive layer 156, 174, and176.

In FIG. 4e , substrate 200 includes core 202 made of an electricallyinsulating material, such as ceramic, glass, or polymer. Core material202 can be one or more laminated layers of prepreg, FR-4, FR-1, CEM-1,or CEM-3 with a combination of phenolic cotton paper, epoxy, resin,woven glass, matte glass, polyester, and other reinforcement fibers orfabrics. Core material 202 is made with thermally conductive material toprovide substrate 200 for effective heat dissipation. Conductive layers204 and 206 are formed over surface 208 of core material 202, andconductive layer 210 is formed over surface 212 of core material 202.Conductive layers 204-206 and 210 are formed using PVD, CVD,electrolytic plating, electroless plating process, evaporation, or othersuitable metal deposition process or metal layer joining with substrate170 through sintering process. Conductive layers 204-206 and 210includes one or more layers of aluminum Al, Cu, Sn, Ni, Au, Ag, Ti, TiW,or other suitable conductive material. Conductive layers 204-206 arepatterned into portions that are electrically common or electricallyisolated depending on the design and function of semiconductor die 104a-104 d. The different portions of conductive layer 204-206 are coupledto bumps 126 a-126 b over interconnect pads 112 a-112 d of semiconductordie 104 a-104 b and external terminals of a leadframe. Substrate 200 ispositioned over and aligned with 3D stacked assembled substrates 198.

FIG. 4f shows substrate 200 mounted to semiconductor die 104 a-104 b tomake 3D stacked assembled substrates 214. The large and smallinterconnect pads 112 a-112 d of FIGS. 3a-3b provide accurate andreliable alignment and mounting of interposer 200 to semiconductor die104 a-104 b. Bumps 126 a-126 b of semiconductor die 104 a-104 b arebonded to conductive layers 204-206 of interposer 200 by a reflowprocess. The temperature and timing of the reflow process, as well asthe bonding material, is selected to prevent debonding back surfaces 108of semiconductor die 104 a-104 d from conductive layer 156, 174, and176, or bumps 126 a-126 b of semiconductor die 104 c-104 d fromconductive layers 160-161 of interposer 150. Semiconductor die 104 a-104d are electrically connected through conductive layers 156 and 160-161and conductive vias 154 of interposer 150, and conductive layers 174-176of substrate 170, and conductive layers 204-206 of substrate 200. Theelectrical interconnect of semiconductor die 104 a-104 d through 3Dstacked assembled substrates 214 reduces signal path length andelectrical parasitic effects.

Heat generated from the operation of semiconductor die 104 a-104 b isdissipated through conductive layers 204-206, core material 202, andconductive layer 210. Heat generated from the operation of semiconductordie 104 c-104 d is dissipated through conductive layers 174-176, corematerial 172, and conductive layer 180. Accordingly, 3D stackedassembled substrates 214 has an internal interposer 150 for electricalinterconnect between semiconductor die 104 a-104 d, and substrates 170and 200 to dissipate heat generated by semiconductor die 104 a-104 dfrom the opposing surfaces of the 3D stacked assembled substrates.

For external electrical interconnect to 3D stacked assembled substrates214, lead 216 is coupled to conductive layer 204 with bump 218, and lead220 is coupled to conductive layer 206 with bump 222. Lead 224 iscoupled to conductive layer 156 with bump 226, and lead 230 is coupledto conductive layer 176 with bump 232. Leads 216, 220, 224, and 230 areexternal terminals of a leadframe. Alternatively, leads 216, 220, 224,and 230 attached to the conductive layers using Ag sintering, metalspray, ultrasonic, or cold weld bonding. When leads 216, 220, 224 and230 are attached by silver sintering, welding, etc., the attachment canbe made before semiconductor die 104 a-104 d are attached to interposer150 and substrates 170 and 20, or simultaneously.

An underfill material 236 is deposited between semiconductor die 104a-104 b and substrate 200 around bumps 126 a-126 b, and underfillmaterial 236 is further deposited between semiconductor die 104 c-104 dand substrate 170 around bumps 126 a-126 b.

In FIG. 4g , an encapsulant or molding compound 240 is deposited overinterposer 150, substrates 170 and 200, and around semiconductor die 104a-104 b as an insulating material using a compressive molding, transfermolding, liquid encapsulant molding, vacuum lamination, spin coating, orother suitable applicator. In particular, encapsulant 240 covers theside surfaces and surface 242 of semiconductor die 104. Encapsulant 240can be high purity polymer composite material, such as epoxy resin withfiller, epoxy acrylate with filler, or polymer with proper filler.Encapsulant 240 is non-conductive and environmentally protects thesemiconductor device from external elements and contaminants.Encapsulant 240 also protects semiconductor die 104 from degradation dueto exposure to light.

The 3D stacked assembled substrates 214 is referred to as IPM 214 with acontrol circuit 164 providing control of the IPM. The 3D stackedassembled substrates 214 is referred to as PIM 214 with a discretesemiconductor device 164. PIM/IPM 214 provides close arrangement ofsemiconductor die 104 a-104 d with electrical connection throughconductive layers 156 and 160-161 and conductive vias 154 of interposer150, and conductive layers 174-176 of substrate 170, and conductivelayers 204-206 of substrate 200. The electrical interconnect ofsemiconductor die 104 a-104 d through PIM/IPM 214 reduces signal pathlength and electrical parasitic effects. In addition, PIM/IPM 214exhibits effective heat dissipation from semiconductor die 104 a-104 dthrough thermally conductive cores 172 and 202 and conductive layers 180and 210 of substrates 170 and 200. The substrates 170 and 200 provideheat dissipation from opposing surfaces of PIM/IPM 214. Substrates 170and 200 electrically isolate internal semiconductor die 104 a-104 d. Thelarge and small interconnect pads 112 a-112 d of FIGS. 3a-3b provideaccurate and reliable alignment and mounting of semiconductor die 104c-104 d to interposer 150 and semiconductor die 104 a-104 b tointerposer 200. The efficient assembly of PIM/IPM 214 reduces packagesize, simplifies manufacturing, increases production, and reduces repairtime.

FIG. 5 shows an embodiment of PIM/IPM 250 with semiconductor die 104a-104 b disposed between substrates 170 and 200, i.e. without interposer150 or semiconductor die 104 c-104 d. Components with a similar functionare assigned the same reference numbers used in FIGS. 4a -4 g. Backsurfaces 108 of semiconductor die 104 a-104 b are mounted to conductivelayers 174 and 176 of substrate 170. The thickness of conductive layers174-176 and 180 of substrate 170 and conductive layers 204-206 and 210of substrate 200 can be selected for optimal heat dissipation. Forexample, conductive layers 174-176 and 180 and conductive layers 204-206and 210 can be made thicker for a thinner semiconductor die 104 a-104 b,respectively. Alternatively, conductive layers 174-176 and 180 andconductive layers 204-206 and 210 can be made thinner for a thickersemiconductor die 104 a-104 b, respectively.

FIG. 6 shows an embodiment of PIM/IPM 260 with semiconductor die 104a-104 b disposed between substrates 170 and 200, i.e. without interposer150 or semiconductor die 104 c-104 d. Components with a similar functionare assigned the same reference numbers used in FIGS. 4a -4 g. Backsurface 108 of semiconductor die 104 a is mounted to conductive layer174 of substrate 170, and back surface 108 of semiconductor die 104 b ismounted to conductive layer 206 of substrate 200. Bumps 126 a-126 b ofsemiconductor die 104 b are connected to conductive layer 176 ofsubstrate 170. The thickness of conductive layers 174-176 and 180 ofsubstrate 170 and conductive layers 204-206 and 210 of substrate 200 canbe selected to accommodate semiconductor die 104 a-104 b of differentthickness. For example, conductive layers 174-176 and 180 and conductivelayers 204-206 and 210 can be made thicker for a thinner semiconductordie 104 a-104 b, respectively, and still maintain the same packageheight. Alternatively, conductive layers 174-176 and 180 and conductivelayers 204-206 and 210 can be made thinner for a thicker semiconductordie 104 a-104 b, respectively, and still maintain the same packageheight.

PIM/IPM 250 and 260 provide close arrangement of semiconductor die 104a-104 b with electrical connection through conductive layers 174-176 ofsubstrate 170, and conductive layers 204-206 of substrate 200. Theelectrical interconnect of semiconductor die 104 a-104 b through PIM/IPM250 and 260 reduces signal path length and electrical parasitic effects.In addition, PIM/IPM 250 and 260 exhibits effective heat dissipationfrom semiconductor die 104 a-104 d through thermally conductive cores172 and 202 and conductive layers 180 and 210 of substrates 170 and 200.The substrates 170 and 200 provide heat dissipation from opposingsurfaces of PIM/IPM 250 and 260. Substrates 170 and 200 electricallyisolate internal semiconductor die 104 a-104 d. The large and smallinterconnect pads 112 a-112 d of FIGS. 3a-3b provide accurate andreliable alignment and mounting of semiconductor die 104 a-104 b tointerposers 170 and 200. The efficient assembly of PIM/IPM 250 and 260reduces package size, simplifies manufacturing, increases production,and reduces repair time.

While one or more embodiments have been illustrated and described indetail, the skilled artisan will appreciate that modifications andadaptations to those embodiments may be made without departing from thescope of the present disclosure.

What is claimed:
 1. A semiconductor device, comprising: a substrate; aplurality of first interconnect pads formed over a surface of thesubstrate; and a plurality of second interconnect pads formed over thesurface of the substrate, wherein the second interconnect pads have anarea different from an area of the first interconnect pads, and thefirst interconnect pads and second interconnect pads are electricallycommon and arranged in an identifiable pattern for alignment.
 2. Thesemiconductor device of claim 1, wherein the identifiable patternincludes rows of the first interconnect pads.
 3. The semiconductordevice of claim 1, wherein the identifiable pattern includes alternatingoffset ones of the first interconnect pads.
 4. The semiconductor deviceof claim 1, wherein the identifiable pattern includes the firstinterconnect pads interposed between the second interconnect pads. 5.The semiconductor device of claim 1, further including a transistorformed within the substrate.
 6. The semiconductor device of claim 1,further includes a plurality of bumps formed over the first interconnectpads and second interconnect pads.
 7. A semiconductor device,comprising: a substrate; and a plurality of interconnect pads formed inan identifiable pattern over a surface of the substrate, wherein firstones of the interconnect pads have an area different from an area ofsecond ones of the interconnect pads.
 8. The semiconductor device ofclaim 7, wherein the interconnect pads are electrically common.
 9. Thesemiconductor device of claim 7, wherein the identifiable patternincludes rows of the interconnect pads.
 10. The semiconductor device ofclaim 7, wherein the identifiable pattern includes alternating offsetones of the interconnect pads.
 11. The semiconductor device of claim 7,wherein the identifiable pattern includes the first ones of theinterconnect pads interposed between the second ones of the interconnectpads.
 12. The semiconductor device of claim 7, further including atransistor formed within the substrate.
 13. The semiconductor device ofclaim 7, further includes a plurality of bumps formed over theinterconnect pads.
 14. A method of making a semiconductor device,comprising: providing a substrate; forming a plurality of firstinterconnect pads over a surface of the substrate; and forming aplurality of second interconnect pads over the surface of the substrate,wherein the second interconnect pads have an area different from an areaof the first interconnect pads, and the first interconnect pads andsecond interconnect pads are arranged in an identifiable pattern. 15.The method of claim 14, wherein the first interconnect pads and secondinterconnect pads are electrically common.
 16. The method of claim 14,wherein the identifiable pattern includes rows of the first interconnectpads.
 17. The method of claim 14, wherein the identifiable patternincludes alternating offset ones of the first interconnect pads.
 18. Themethod of claim 14, wherein the identifiable pattern includes the firstinterconnect pads interposed between the second interconnect pads. 19.The method of claim 14, further including forming a transistor withinthe substrate.
 20. The method of claim 14, further includes forming aplurality of bumps over the first interconnect pads and secondinterconnect pads.